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Name tensor axis dims in the graph view, memory sharing and operator types in the hardware IR - #162
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Stream AIE Metrics Regression Guard⚠ 7 cell(s) flagged (total_latency > 0.1% tol): hardware_swiglu[fusemax], hardware_two_conv[eyeriss_like_dual_core], hardware_two_conv[eyeriss_like_quad_core], hardware_two_conv[fusemax], hardware_two_conv[meta_prototype], hardware_two_conv[simba_small], hardware_two_conv[tpu_like_quad_core] 16 of 16 cells captured Provenance: baseline hardware_swiglu — 8 hardware (⚠ 1 flagged)
hardware_two_conv — 8 hardware (⚠ 6 flagged)
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…mory and a core's operators in the hardware IR
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Stacked on #161.
TensorRefIRgainsdims: per tensor axis, the unique dims it spans, written as the nodes'dimsare. An edge reads its tensor through the producer, so an intermediate's axes are the producer's output dims. A graph input reads through its consumer, so a conv input shows its windows, e.g.(z5 + z1) - 1.core_memory_sharing, the groups of cores that share one top-level memory, next tonb_shared_mem_groups.operator_types, None on a generic core.CoreIR.row_idandcol_idaccept None. A ZigZag core has no grid position, soAcceleratorIR.from_internalfailed on every ZigZag accelerator.All new fields default to empty, so existing readers are unaffected. Fast suite: 913 passed.